HP PA-8600

Configuration

HP PA-8600. HP J6000, 278-pin 120MHz ECC SDRAM DIMMs.

HP PA-8600, 250 nm, 5-layer metal CMOS, 21.3 * 22.0 mm2 die, 140,000,000 FETs, 5-layer metal CMOS packaged in a 544-pin LGA package.

CONS: PA-RISC doesn't support Multiply operation with integer registers. So compiler can produce the sequence of instructions for just one integer Multiply: the transfer operands from integer registers to float registers (via memory), float register Multiply, and the transfer of result from float register to integer register.

4 KB pages mode

Size Latency Description
640 KB 3 TLB + Cache
1 MB 3 + 200 ns + 200 ns (TLB miss)
... 3 + 380 ns + 180 ns (RAM access)

Pipeline

Integer pipeline:

# Name Description
1 IF0 Instruction Fetch
2 IF1
3 DEC Instruction Decode
4 QU Insert in I-Queue
5 ARB Arbitrate
6 EX / AC Execute / Address Calculate
7 WB / DC0 Write Result / Data Cache 0
8 / DC1 / Data Cache
9 / WB / Write Result

Links

PA-RISC at Wikipedia

PA-8000 at Wikipedia

PA-RISC Processors at OpenPA.net