AMD Am486

AMD Am486DX2 (80 MHz). NV8T, WT, L2 256 KB SRAM 15ns 2-1-1-1, SiS 496/497. RAM: 16 MB (8 MB x 2 async DRAM 70ns)

• L1 cache = 8 KB, 16 B/line, 4-WAY.
• L2 cache = 256 KB, 64 B/line, 8-WAY, SRAM
• L3 cache = 8 MB, 64 B/line, 16-WAY

• TLB: 32 entries, 4-way. pseudo-LRU. LRU 3 bits per set. TLB entry: 20 phy bits / 17 virtual bits.

• L1 Cache Latency = 2 cycles for simple access via pointer
• L1 Cache Latency = 2 cycles for access with complex address calculation (size_t n, *p; n = p[n]).
• L2 Cache Latency = 16 cycles
• RAM Latency = 29 cycles (362 ns) sequential at same DRAM page

4 KB pages

• Data TLB L1 size = 32 items. 4-WAY. Miss penalty = 8 cycles. Parallel miss: 11 cycle per access

  Size        Latency       Increase   Description

   4 K     2                           
   8 K     3                       1    
  16 K    10                       7   + 14 (L2)
  32 K    13                       3   
  64 K    21                       8   
 128 K    28                       7   
 256 K    31                       3   + 8 (TLB miss), + DRAM
 512 K    35                       4   
   2 M    41                       6
   4 M    46                       5
   8 M    50                       6   + 8 (page walk to L2)        

• 4-bytes range cross penalty = 3 cycles.
• L2 Read B/W (16 bytes step) = 43 MB/s
• RAM Read B/W (4 bytes step) = 27 MB/s
• RAM Read B/W (16 bytes step) = 43 MB/s
• Cache/RAM Write B/W (4 bytes step) = 50 MB/s

Links

AMD Am486 at Wikipedia