AMD Bobcat (Zacate)

Configuration

AMD E-350 1600 MHz.

• L1 Data cache = 32 KB. 64 B/line, 8-WAY. Parity Protected, Copyback, Advanced 8-stream prefetcher.
• L1 Instruction cache = 32 KB, 64 B/line, 2-WAY, Parity Protected. Fetch up to 32 bytes per cycle.
• L2 cache size = 512 KB. 64 B/line, 16-WAY. ECC protected, Half speed clocking for power reduction.
• dual x86 instruction decoder: Scans up to 22 bytes, Decodes up to 2 x86 instructions per cycle, The decoder can directly map 89% of x86 instructions to a single microOp, an additional 10% to a pair of microOps, and more complicated x86 instructions (<1%) are microcoded (Dynamic Instruction Counts).
• Branch Predictor: Predicts up to two branches per cycle, Remembers branch instruction locations, Return Stack Address Predictor, Indirect Dynamic Address Predictor.
• 2 ALU, LOAD, STORE, 2 * FPU.
• Integer Execution: A dual port integer scheduler feeds 2 ALUs, A dual port address scheduler feeds a load address unit, and a store address unit. Physical Register File uses maps and pointers to reduce power by minimizing data copying/movement.
• FPU: A centralized FP scheduler feeds two 64-bit FP execution stacks, MMX and Logical units are replicated in both stacks, The FP Mul Unit can perform 2 SP multiplies per cycle, The FP Add Unit can perform 2 SP additions per cycle, A physical register file is used to reduce power.
• Out-of-Order Load Store Unit: Loads bypassing loads, Loads bypassing stores, Stores bypassing loads, Bypass tracking and dependency correction, Hazard predictor, Fast store forwarding, Fast critical word fill forwarding.
• 64-bit DDR3.
• Bus Unit: 8-outstanding data accesses, 2-outstanding fetch accesses, Eviction Buffers, Fill Buffers, Write combining buffers, Coherency management.

4 KB pages mode (64-bit Windows, 64-bit soft)

• DATA L1 TLB size = 40 items. Miss penalty = ?.
• DATA L2 TLB size = 512 items. Miss penalty = ?.
• Instruction TLB size = 512 items.

2 MB pages mode (64-bit Windows, 64-bit soft)

• DATA L1 TLB size = 8 items. Miss penalty = ?.
• DATA L2 TLB size = 64 items. Miss penalty = ?.
• Instruction TLB size = 8 items.

Integer pipeline:

Links

Bobcat at Wikipedia

Bobcat. AMD's New Low Power x86 Core Architecture. Brad Burgess. Hot Chips.