Intel Goldmont

Intel Pentium N4200 (Goldmont), 2.5 GHz (Turbo Boost), 14 nm. 6W TDP. RAM: 2 + 4 GB.

L1 Data Data cache = 24 KB. 64-byte line. 6-way.
L1 Instruction cache: 32 KB, 64-byte line, 8-way.
L2 Cache: 1024 KB (per 2 cores), 64-byte line, 16-way. Probably 2 lines are loaded from RAM for read access.

Instruction TLB L1I 4K: 48 entries, full-assoc.

The decoder can decode 3 instructions per cycle.
The microcode sequencer can send 3 uops per cycle for allocation into the reservation stations.
Retirement supports a peak rate of 3 per cycle.
L2 Predecode Cache: 16K
Max Throughput of Decoders: 20 Bytes per cycle
Loop stream: 27 instructions (or uops?)
Addressing 39-bit physical, 48-bit linear.

L1 Data Cache Latency = 3 cycles for simple access via pointer
L1 Data Cache Latency = 3 cycles for access with complex address calculation (size_t n, *p; n = p[n]).
L2 Cache Latency = 17 cycles
RAM Latency = 17 cycles + 110 ns (maybe another n4200 systems can be faster for RAM).

2 MB pages mode (64-bit Windows)

DATA TLB L0D 4KB: 32 entries, full-assoc. Miss penalty = 7 cycles. Parallel miss: 3 cycles per access
DATA TLB L1D 2MB: 32 entries, 4-way. Miss penalty = 32-60 cycles. Parallel miss: 32 cycles per access

  Size        Latency       Increase   Description

  24 K     3                           
  32 K     7                       4   + 14 (L2)        
  64 K    12                       5   
 128 K    15                       3   
 256 K    19                       4   + 7 (L0 TLB miss)
 512 K    22                       3   
   1 M    23                       1   
   2 M    24 +  62 ns      1 + 62 ns   + 110 ns (RAM)
   4 M    24 +  88 ns        + 26 ns   
   8 M    24 + 100 ns        + 12 ns   
  16 M    24 + 106 ns        +  6 ns   
  32 M    24 + 109 ns        +  3 ns   
  64 M    24 + 110 ns        +  1 ns   
 128 M    54 + 110 ns     30           + 60 (L1 TLB miss)
 256 M    69 + 110 ns     15        
 512 M    77 + 110 ns      8     
   1 G    82 + 110 ns      5

4 KB pages mode (64-bit Windows)

DATA TLB L0D 4KB: 32 entries, full-assoc. Miss penalty = 7 cycles. Parallel miss: 3 cycles per access
DATA TLB L1D 4KB: 512 entries, 4-way. Miss penalty = 20-50 cycles. Parallel miss: 30 cycles per access
PDE cache = ? items. Miss penalty = ? cycles.

  Size        Latency       Increase   Description

  24 K     3                           
  32 K     7                       4   + 14 (L2)        
  64 K    12                       5   
 128 K    15                       3   
 256 K    19                       4   + 7 (L0 TLB miss)
 512 K    22                       3   
   1 M    23                       1   
   2 M    24 +  62 ns      1 + 62 ns   + 110 ns (RAM)
   4 M    40 +  88 ns     16 + 26 ns   + 50 (L1 TLB miss)
   8 M    55 + 100 ns     15 + 12 ns   
  16 M    67 + 106 ns     12 +  6 ns   
  32 M    80 + 109 ns     13 +  3 ns   
  64 M   110 + 120 ns     30 + 11 ns   + ? (PDE cache miss)
 128 M   125 + 160 ns     15 + 40 ns
 256 M   135 + 180 ns     10 + 20 ns   + 110 ns (Page walk to RAM)
 512 M   140 + 200 ns      5 + 20 ns
   1 G   140 + 210 ns        + 10 ns

MISC

Branch misprediction penalty = 13-14 cycles

64-bytes range cross penalty = 6 cycles
4096-bytes range cross penalty = 9 cycles

L1 B/W (Parallel Random Read) = 1 cycles per one access

L2->L1 B/W (Parallel Random Read) = 3.3 per cache line
L2->L1 B/W (Read, 64 bytes step) = 3.3 cycles per cache line
L2->L1 B/W (Read, 64 bytes step - pointer chasing) = 13.5 cycles per cache line
L2->L1 B/W (Read, 128 bytes step - pointer chasing) = 17.0 cycles per cache line
L2 Write (Write, 64 bytes step) = 8 cycles per write (cache line)

RAM Read B/W (Parallel Random Read) = 16 ns / access.
RAM Read B/W (Read, 8 Bytes step) = 6400 MB/s
RAM Read B/W (Read, 64-128 Bytes step - pointer chasing) = 5900 - 6200 MB/s (HW prefetch)
RAM Write B/W (Write, 8 Bytes step) = 5700 MB/s

7-Zip Benchmark

Turbo Boost, 2500 MHz.

Note: MIPS and Effectiveness values are normalized with AMD K8 cpu.


7za b -mm=* -mmt1

7-Zip [64] 16.04 : Copyright (c) 1999-2016 Igor Pavlov : 2016-10-04

Intel(R) Pentium(R) CPU N4200 @ 1.10GHz (506C9)
CPU Freq:  4000  2064  2064  4000  2064  2723  2337  2522  2426

RAM size:    5713 MB,  # CPU hardware threads:   4
RAM usage:    225 MB,  # Benchmark threads:      1


Method           Speed Usage    R/U Rating   E/U Effec
                 KiB/s     %   MIPS   MIPS     %     %

CPU                      100   2464   2464
CPU                      100   2464   2465
CPU                      100   2464   2464   100   100

LZMA:x1           8258    98   3067   3019   124   123
                 28444   100   2316   2316    94    94
LZMA:x5:mt1       1572   100   1964   1964    80    80
                 25935   100   2188   2188    89    89
LZMA:x5:mt2       3404   193   2209   4253    90   173
                 26029    99   2211   2196    90    89
Deflate:x1       20971   100   2663   2663   108   108
                 79676   100   2476   2476   100   100
Deflate:x5        7037   100   2710   2710   110   110
                 79696   100   2474   2474   100   100
Deflate:x7        2582   100   2862   2861   116   116
                 80334   100   2493   2493   101   101
Deflate64:x5      6432   100   2780   2780   113   113
                 79371   100   2483   2483   101   101
BZip2:x1          3868   100   2338   2337    95    95
                 20014   100   2169   2170    88    88
BZip2:x5          2730   100   2279   2279    92    92
                  9679    99   1911   1900    78    77
BZip2:x5:mt2      4854   194   2089   4051    85   164
                 16216   170   1877   3183    76   129
BZip2:x7           887   100   2304   2300    94    93
                  9767   100   1916   1915    78    78
PPMD:x1           2888   100   2988   2987   121   121
                  1659   100   1954   1954    79    79
PPMD:x5           1605   100   2721   2721   110   110
                  1106   100   2073   2073    84    84
Delta:4         381658   100   2345   2345    95    95
                370635   100   2277   2277    92    92
BCJ             699881   100   2880   2867   117   116
                700084   100   2867   2868   116   116
AES256CBC:1     101030   100   2483   2483   101   101
                 95770   100   2362   2354    96    96
AES256CBC:2     434950   100   3564   3563   145   145
               1144999   100   2345   2345    95    95
CRC32:1         404822   100   2947   2947   120   120
CRC32:4        1058393   100   2362   2362    96    96
CRC32:8        1817056   100   2464   2464   100   100
CRC64           956552   100   1959   1959    80    80
SHA256          102367   100   2088   2088    85    85
SHA1            226924   100   2124   2124    86    86
BLAKE2sp        145460   100   3201   3200   130   130

CPU                      100   2459   2459
------------------------------------------------------
Tot:                     112   2304   2570    93   104

Links

Intel Goldmont at Wikipedia