Intel Ice Lake

Intel i7-1065G7 (Ice Lake), 3.9 GHz (Turbo Boost), 10 nm. 122 mm2, RAM: 16 GB, dual LPDDR4-3733. Surface Pro 7

L1 Data cache = 48 KB, 64 B/line, 12-WAY ?.
L1 Instruction cache = 32 KB, ? B/line, ?-WAY.
L2 cache = 512 KB, 64 B/line, 8-WAY
L3 cache = 8 MB, 64 B/line, 16-WAY

Data TLB L1 (stores): 16 entries, 16-way. Shared for all page sizes
Instruction TLB 4KB: 128 entries (64 per thread MT), 8-way.
Instruction TLB 2MB: 16 entries (8 per thread MT), 8-way.

L1 Data Cache Latency = 5 cycles for simple access via pointer
L1 Data Cache Latency = 5 cycles for access with complex address calculation (size_t n, *p; n = p[n]).
L2 Cache Latency = 13 cycles
L3 Cache Latency = 42 cycles (core 0)
L3 Cache Latency = 41 cycles (core 1)
L3 Cache Latency = 41 cycles (core 2)
L3 Cache Latency = 42 cycles (core 3)
RAM Latency = 42 cycles + 87 ns (LPDDR4-3733)
RAM Latency = 42 cycles + 64 ns (DDR4-2666 19-19-19)

Note: It's possible that L3 cache is victim (non-inclusive) cache of L2. Also the page table walks that miss L2 cache are slow. Probably the cores don't use L3 cache for page tables in most cases.

1 GB pages

Data TLB L1 (loads): 8 entries, 4-way.
L2 TLB: 1024 entries, 8-way. Shared with 4 KB pages TLB

  Size        Latency       Increase   Description

  48 K     5                           
  64 K     7                       2   + 8 (L2)        
 128 K    10                       3   
 256 K    11                       1
 512 K    12                       1   
   1 M    28                      16   + 29 (L3)
   2 M    35                       7
   4 M    39                       4
   8 M    42                       3
  16 M    42 + 50 ns           50 ns   + 87 ns (RAM)
  32 M    42 + 70 ns           20 ns
  64 M    42 + 79 ns            9 ns
 128 M    42 + 83 ns            4 ns   
 256 M    42 + 85 ns            2 ns
 512 M    42 + 86 ns            1 ns 
1024 M    42 + 87 ns            1 ns

2 MB pages mode (64-bit Windows)

Data TLB (loads): 32 items (4-way). Miss Penalty = 7 cycles. Parallel miss: ? cycles per access
L2 TLB: 1024 items, 8-way. Shared with 4 KB pages TLB. Miss Penalty = ? cycles.

  Size        Latency       Increase   Description

  48 K     5                           
  64 K     7                       2   + 8 (L2)        
 128 K    10                       3   
 256 K    11                       1
 512 K    12                       1   
   1 M    28                      16   + 29 (L3)
   2 M    35                       7
   4 M    39                       4
   8 M    42                       3
  16 M    42 + 50 ns           50 ns   + 87 ns (RAM)
  32 M    42 + 70 ns           20 ns
  64 M    42 + 79 ns            9 ns
 128 M    46 + 83 ns        4 + 4 ns   + 7 (L1 TLB miss)
 256 M    48 + 85 ns        2 + 2 ns
 512 M    49 + 86 ns        1 + 1 ns 
1024 M    49 + 87 ns            1 ns

4 KB pages mode (64-bit Windows)

Data TLB L1 (loads): 64 items. 4-way. Miss penalty = 7 cycles. Parallel miss: ? cycle per access
Data TLB L2: 2048 items. 16-way. Miss penalty = 30 ? cycles. Parallel miss: ? cycles per access
PDE cache = ? items. Miss penalty = ? cycles.

  Size        Latency       Increase   Description

  48 K     5                           
  64 K     7                       2   + 8 (L2)        
 128 K    10                       3   
 256 K    11                       1
 512 K    16                       5   + 7 (L1 TLB miss)
   1 M    33                      17   + 29 (L3)
   2 M    41                       8
   4 M    45                       4
   8 M    49 +  9 ns               4
  16 M    69 + 50 ns      20 + 41 ns   + 30 (L2 TLB miss) + 87 ns (RAM)
  32 M    77 + 70 ns       8 + 20 ns
  64 M    81 + 79 ns       4 +  9 ns
 128 M    99 + 83 ns      18 +  4 ns   PDE cache miss ?
 256 M   107 + 96 ns       8 + 14 ns
 512 M   111 +127 ns       4 + 31 ns 
1024 M   115 +147 ns       4 + 20 ns   + ? ns Page walk to L3 and RAM
2048 M   115 +155 ns         +  8 ns   
4096 M   115 +159 ns         +  4 ns

MISC

Branch misprediction penalty = 17 cycles average (if mOp cache hit).
Branch misprediction penalty = 20-21 ? cycles (if mOp cache miss).

64-bytes range cross penalty = 6 cycles
4096-bytes range cross penalty = 7 cycles (1 additional cycle over 64-bytes cross penalty).

L1 B/W (Parallel Random Read) = 0.5 cycles per one access
L1 Write (8-32 bytes step) = 0.5 cycles per one write

L2->L1 B/W (Parallel Random Read) = 1.4 cycles per cache line
L2->L1 B/W (Read, 64 bytes step) = 1.4 cycles per cache line
L2 Write (Write, 16-64 bytes step) = 3.0 cycles per cache line

L3->L1 B/W (Parallel Random Read) = 4.0 (or less) cycles per cache line
L3->L1 B/W (Read, 64 bytes step) = 3.3 cycles per cache line
L3 Write (Write, 16-64 bytes step) = 5.2 cycles per cache line

RAM Read B/W (Parallel Random Read) = 6 ns (or less) / cache line
RAM Read B/W (Read, 16-64 Bytes step) = 24-25 GB/s
RAM Read B/W (Read, 64 Bytes step - pointer chasing) = 18 GB/s
RAM Write B/W (Write, 8-64 Bytes step) = 18 GB/s

7-Zip Benchmark

Notes:

7z b -mm=* : MIPS and Effectiveness values are normalized with AMD K8 cpu.


7-Zip 19.02 alpha (x64) : Copyright (c) 1999-2019 Igor Pavlov : 2019-09-05

 m=* mt=*
Windows 10.0 18363 Suite:100 Type:1
x64 6.7E05 cpus:8 128T f:310F2774C
Intel(R) Core(TM) i7-1065G7 CPU @ 1.30GHz (706E5)
CPU Freq:  3818  3637  3732  3747  3776  3746  3687  3752

RAM size:   15978 MB,  # CPU hardware threads:   8
RAM usage:    225 MB,  # Benchmark threads:      1


Method           Speed Usage    R/U Rating   E/U Effec
                 KiB/s     %   MIPS   MIPS     %     %

CPU                      100   3754   3756
CPU                      100   3754   3745
CPU                      100   3725   3731   100   100

LZMA:x1          25930    99   9583   9479   257   254
                 79043   101   6388   6436   171   173
LZMA:x5:mt1       4422   100   5527   5525   148   148
                 78415   100   6600   6614   177   177
LZMA:x5:mt2      12151   190   7988  15181   214   407
                 79041   100   6700   6667   180   179
Deflate:x1       58070   100   7339   7374   197   198
                173188   100   5399   5381   145   144
Deflate:x5       17619   100   6785   6784   182   182
                175116   100   5425   5436   145   146
Deflate:x7        7164   100   7957   7938   213   213
                176201   101   5423   5468   145   147
Deflate64:x5     16117   100   6971   6965   187   187
                175614   100   5498   5493   147   147
BZip2:x1          9564    99   5812   5779   156   155
                 55047   100   5943   5967   159   160
BZip2:x5          8772   100   7354   7321   197   196
                 42100    99   8315   8263   223   221
BZip2:x5:mt2     15461   193   6680  12904   179   346
                 64949   155   8232  12747   221   342
BZip2:x7          2547   100   6594   6600   177   177
                 42515   100   8308   8337   223   223
PPMD:x1           7703   100   7974   7967   214   214
                  6571   100   7718   7738   207   207
PPMD:x5           5354   100   9067   9075   243   243
                  4578   100   8618   8580   231   230
Delta:4        1425363   100   8762   8757   235   235
               1183031   101   7181   7269   192   195
BCJ            1955931    99   8093   8011   217   215
               1947021   100   7959   7975   213   214
AES256CBC:1     260248   100   6367   6396   171   171
                262581   100   6453   6453   173   173
AES256CBC:2    1267544   100  10381  10384   278   278
               6985676   100   7181   7153   192   192
AES256CBC:3    1284417   100  10495  10522   281   282
              12072366   100  12403  12362   332   331
CRC32:1         525428   100   3820   3825   102   103
CRC32:4        1437441    99   3226   3208    86    86
CRC32:8        2932494   100   3979   3976   107   107
CRC64          1451072   100   2966   2972    80    80
SHA256:1        322897   100   6586   6587   177   177
SHA256:2       1444531   100   3061   3062    82    82
SHA1:1          683021   100   6409   6393   172   171
SHA1:2         1731578   100   3473   3463    93    93
BLAKE2sp        448120   100   9845   9859   264   264

CPU                      100   3769   3771
------------------------------------------------------
Tot:                     112   6834   7761   186   208

Links

Ice Lake at Wikipedia

Ice Lake at WikiChip