Ingenic JZ4780

Ingenic JZ4780 (XBurst MIPS32 little endian, 2 cores), 1200 MHz, 1 GB (32-bit DDR3). MIPS Creator CI20.

• L1 Data cache = 32 KB. 32 B/line. 8-way.
• L1 Instruction cache = 32 KB. 32 B/line. 8-way.
• ITLB size = 8 items. (2 pages per item),
• DTLB size = 8 items. (2 pages per item),
• joint-TLB = 32 items (2 pages per item),
• L2 cache = 512 KB. 128 B/line (or prefetching 256 B/line ?).

• L1 Data cache latency = 4 cycles.
• MIPS ISA doesn't support complex address modes in LOAD instruction. The latence for LOAD from integer array (n=p[n]) is 6 cycles.
• L2 Data cache latency = 32 cycles.
• RAM Latency = 32 cycles + 170 ns
• DTLB miss penalty = 3 cycles
• joint-TLB miss penalty = 67 cycles

4 KB pages

  32 K     4                             TLB + L1
  64 K    19               15            +28 (L2)
 128 K    27                8            +3 (DTLB miss)        
 256 K    40               13           
 512 K    80 +  35 ns      40 + 35 ns    +67 (joint-TLB miss)        
   1 M    92 + 108 ns      12 + 73 ns    +170 ns (RAM)
   2 M    97 + 140 ns       5 + 32 ns               
   4 M   100 + 156 ns       3 + 16 ns               
   8 M   102 + 170 ns       2 + 14 ns     
  16 M   102 + 179 ns            9 ns    
  32 M   102 + 183 ns            4 ns     
  64 M   102 + 191 ns            8 ns     
 128 M   102 + 208 ns           17 ns     
 256 M   102 + 250 ns           42 ns    + ??? ns (Page walk to RAM) 
 512 M   102 + 295 ns           45 ns     

• 4-bytes range cross penalty = 356 cycles

• L1 B/W (Parallel Random Read) = 1 cycle per one access
• L1 Write = 1 cycle per write

• L2->L1 B/W (Parallel Random Read) = 32 cycles per access (or 16 cycles per access in some cases)
• L2->L1 B/W (Read, 32 bytes step) = 32 cycles per cache line (32 bytes)
• L2 Write (Write, 4 bytes step) = 6 cycles per write
• L2 Write (Write, 32 bytes step) = 40 cycles per write (32 cache line, Write Allocate in L1 ?)

• RAM Read B/W (Parallel Random Read) = no parallel accesses, or 2 parallel accesses in some cases.
• RAM Read B/W (Read, 4 Bytes step) = 460 MB/s
• RAM Read B/W (Read, 128 Bytes step) = 1100 MB/s
• RAM Read B/W (Read, 256 Bytes step) = 1250 MB/s

• RAM Write (4 Bytes step) = 490 MB/s
• RAM Write (128 Bytes step) = 730 MB/s
• RAM Write (256 Bytes step) = 900 MB/s

Branch misprediction penalty = 3 cycles.

Links

Ingenic