MIPS 4K

TI AR7 (MIPS 4KEc) 150 MHz

L1 Data cache = 16 KB. 16 B/line. 4-way, Write-through, no write-allocate, virtually indexed, physically tagged. The replacement policy is least recently filled (LRF).
16 dual-entry fully associative TLB, 2 virtual pages (odd and even) per entry. 4K/16K/64K/256K/1M/4M/16M pages.

4 KB pages mode

#	Name	Description
1	Instruction	I-TLB translation. An instruction is fetched from the ICache.
1	Instruction	An instruction is fetched from the ICache.
2	Execution	Instruction decode. Operands are fetched from the register file. Instruction logic selects an instruction address.
2	Execution	ALU operation begins. ALU calculates the data virtual address for load and store instructions. ALU resolves branch conditions and calculates branch target address. Instruction logic selects an instruction address.
3	Memory	ALU operation completes. Data TLB and data cache lookup. The data cache fetch and VA->PA translation.
3	Memory	The data cache fetch and VA->PA translation.
4	Align / Accumulate	A separate aligner aligns loaded data with its word boundary.
4	Align / Accumulate	.
5	Writeback	Result is written back to the register file.
5	Writeback	.