Cavium Octeon II

Cavium Octeon II, 1.0 GHz, 2 cores, (CN6120 ?, 64 nm ?). 2 GB DDR3, Ubiquiti EdgeRouter PRO.

• L1 Data cache = 32 KB, 128 B/line, 32-WAY. Write-Through.
• L1 Instruction cache = 37 KB, ? B/line, 37-WAY.
• L2 Cache = 1 MB, 128 B/line, ?-WAY, shared by all cores. Write-Back.

• Jump Prediction (256 entrires)
• Branch Prediction (2048 * 2)
• Write Buffer (2 KB, 16-Entry)

• L1 Data Cache Latency = 3 cycles for simple access via pointer
• L1 Data Cache Latency = 5 cycles for access with complex address calculation (size_t n, *p; n = p[n]). MIPS ISA doesn't support complex address modes in LOAD instruction.
• L2 Cache Latency = 28 cycles
• RAM Latency = 28 cycles + 88 ns

• 2-wide issue?
• Pipe 0 : ALU / Shift / Load Store
• Pipe 1 : ALU / Shift / MUL / COP2 / Branch / Jump

4 KB pages, n32 ABI

• DTLB size = 128 items, 2 pages per item, Miss penalty = 35 cycles.

  Size        Latency       Increase   Description

  32 K     3                           
  64 K    16                      13   + 25 (L2)        
 128 K    22                       6   
 256 K    25                       3
 512 K    26                       1   
   1 M    30 +  4 ns       4 +  4 ns
   2 M    46 + 45 ns      16 + 41 ns   + 35 (TLB miss) + 88 ns (RAM)
   4 M    57 + 67 ns      11 + 22 ns  
   8 M    63 + 82 ns       6 + 15 ns  
  16 M    63 + 97 ns           15 ns  
  32 M    63 + 106 ns           9 ns  
  64 M    63 + 111 ns           5 ns 
 128 M    63 + 119 ns           8 ns
 256 M    63 + 142 ns          23 ns   + ? ns (Page walk to RAM ?) 
 512 M    63 + 166 ns          24 ns  
1024 M    63 + 184 ns          18 ns   

2 MB pages (THP), n32 ABI

• DTLB size = 128 items ?, Miss penalty = ? cycles.

  Size        Latency       Increase   Description

  32 K     3                           
  64 K    16                      13   + 25 (L2)        
 128 K    22                       6   
 256 K    25                       3
 512 K    26                       1   
   1 M    27                       1
   2 M    28 + 45 ns       1 + 45 ns   + 88 ns (RAM)
   4 M    28 + 67 ns           22 ns  
   8 M    28 + 78 ns           11 ns  
  16 M    28 + 83 ns            5 ns  
  32 M    28 + 86 ns            3 ns  
  64 M    28 + 88 ns            
 128 M    28 + 88 ns            
 256 M    28 + 88 ns            
 512 M    28 + 137 ns          49 ns   + ? ns (TLB miss) 

MISC

• Branch misprediction penalty = 6 cycles

• 8-bytes range cross penalty = 10 cycles
• Page cross - no additional penalty

• L1 B/W (Parallel Random Read) = 1 cycle per one access

• L2->L1 B/W (Parallel Random Read) = 28 cycles per cache line (no parallel access)
• L2->L1 B/W (Read, 128 bytes step) = 28 cycles per cache line (no HW prefetch L2->L1)

• RAM Read B/W (Parallel Random Read) = 28 cycles + 88 ns / access (no parallel access)
• RAM Read B/W (Read, 8-128 Bytes step) = 1100 MB/s (no HW prefetch from RAM)
• RAM Write B/W (Write, 4-128 Bytes step) = 3500 MB/s

Pipeline

Integer pipeline:

7-Zip Benchmark

Linux-4.1 (THP on), gcc-5 -O2 -march=octeon2 -mabi=n32

Note: MIPS and Effectiveness values are normalized with AMD K8 cpu.

7z b -mm=* -mmt1

7-Zip (a) 15.09 beta : Copyright (c) 1999-2015 Igor Pavlov : 2015-10-16
p7zip Version 15.09 beta (locale=en_US.UTF-8,Utf16=on,HugeFiles=on,32 bits,2 CPUs LE)

LE
CPU Freq:   996   997   999   870   980   999   999   994

RAM size:    1960 MB,  # CPU hardware threads:   2
RAM usage:    225 MB,  # Benchmark threads:      1


Method           Speed Usage    R/U Rating   E/U Effec
                 KiB/s     %   MIPS   MIPS     %     %

CPU                      100   1001    998
CPU                      100    998    997
CPU                      100   1001    999   100   100

LZMA:x1           2606   100    954    953    95    95
                 10317   100    842    840    84    84
LZMA:x5:mt1        689   100    862    862    86    86
                 10031   100    848    846    85    85
LZMA:x5:mt2        951   142    835   1188    84   119
                 10001   100    848    844    85    84
Deflate:x1        5600   100    710    711    71    71
                 23965   100    745    745    75    75
Deflate:x5        2194   100    846    845    85    85
                 24006   100    746    745    75    75
Deflate:x7         735   100    816    815    82    82
                 24122   100    749    749    75    75
Deflate64:x5      2096   100    907    906    91    91
                 23794   100    744    744    74    74
BZip2:x1          1045   100    632    632    63    63
                  5398   100    585    585    59    59
BZip2:x5           840   100    701    701    70    70
                  4104   100    806    806    81    81
BZip2:x5:mt2      1526   192    662   1274    66   127
                  6648   172    757   1305    76   131
BZip2:x7           251   100    651    651    65    65
                  4122   100    809    808    81    81
PPMD:x1            617   100    639    639    64    64
                   490   100    578    578    58    58
PPMD:x5            463   100    787    785    79    79
                   371   100    696    696    70    70
Delta:4          79818   100    490    490    49    49
                 78328   100    481    481    48    48
BCJ             124391   100    509    510    51    51
                124515   100    511    510    51    51
AES256CBC:1      23722   100    583    583    58    58
                 24947   100    613    613    61    61
AES256CBC:2 

CRC32:1         119151   100    867    867    87    87
CRC32:4         247670   100    553    553    55    55
CRC32:8         305149   100    414    414    41    41
CRC64           248140   100    508    508    51    51
SHA256           31608   100    644    645    64    65
SHA1             67986   100    636    636    64    64
BLAKE2sp         45853   100   1009   1009   101   101

CPU                      100    998    999
------------------------------------------------------
Tot:                     107    785    840    79    84