Intel Pentium MMX

• L1 Data cache = 16 KB. 32 B/line. 4-Way
• L1 Instruction cache = 16 KB. 32 B/line, 4-WAY.
• L1 B/W (Parallel Random Read) = 0.62 cycles per one access

Intel Pentium MMX 200 MHz

Intel Pentium MMX 200 MHz (100 * 2) + 128 MB (PC-133 CL2 @ 100MHz). via MVP3, L2 512 KB.

• L2 cache size = 512 KB. direct-mapped. 32-byte line size. Latency = 2 + 50 ns
• RAM latency = 2 + 50 ns + 54 ns (for open RAM page). Open RAM page size is 2 KB?
• RAM latency = 2 + 50 ns + 54 ns + 60 ns (for new RAM page)

4 MB pages mode (linux)

TLB size = 64 items.

  Size        Latency       Increase   Description

  16 K     2
  32 K     2 +  25 ns          25 ns   + 50 ns (L2 cache)
  64 K     2 +  38 ns          13 ns           
 128 K     2 +  44 ns           6 ns
 256 K     2 +  47 ns           3 ns
 512 K     2 +  49 ns           2 ns   
   1 M     2 + 110 ns          61 ns   + 114 ns (RAM)
   2 M     2 + 139 ns          29 ns
   4 M     2 + 151 ns          12 ns
   8 M     2 + 157 ns           6 ns   
  16 M     2 + 160 ns           3 ns   
  32 M     2 + 162 ns           2 ns
  64 M     2 + 163 ns           1 ns

• L2->L1 B/W (Random Read) = 12 cycles (2 + 50 ns) per cache line (32-bytes) = 533 MB/s
• L2->L1 B/W (Read, 32 bytes step) = 12 cycles (2 + 50 ns) cycles per cache line (32-bytes) = 533 MB/s
• RAM Read B/W (Random Read) = 2 + 164 ns / cache line = 184 MB/s
• RAM Read B/W (Read, 4 Bytes step) = 170 MB/s
• RAM Read B/W (Read, 32 Bytes step) = 2 + 104 ns / cache line (32-bytes line) = 280 MB/s
• L1/L2/RAM Write = 10 cycles (50 ns) per write = 80 MB/s

4 KB pages mode (linux)

TLB size = 64 items. TLB miss penalty = 4 cycles + 100 ns

  Size        Latency       Increase   Description

  16 K     2
  32 K     2 +  25 ns          25 ns   + 50 ns (L2 cache)
  64 K     2 +  37 ns          12 ns           
 128 K     2 +  54 ns          17 ns            
 256 K     2 +  68 ns          14 ns
 512 K     4 + 140 ns      2 + 72 ns   + 4 + 100 ns (TLB miss to L2)
   1 M     5 + 190 ns      1 + 50 ns   + 114 ns (RAM)
   2 M     6 + 223 ns      1 + 33 ns
   4 M     6 + 245 ns        + 22 ns
   8 M     6 + 258 ns          13 ns   
  16 M     6 + 265 ns           7 ns   
  32 M     6 + 273 ns           8 ns
  64 M     6 + 284 ns          11 ns   + (Page walk to RAM) ?

Intel Pentium MMX 166 MHz

Intel Pentium MMX 166 MHz + 128 MB (PC-133 CL2 @ 66MHz) (only first 64 were used). i430TX.

• L2 cache size = 512 KB. direct-mapped? 32-byte line size. Latency = 2 + 60 ns
• L1/L2/RAM Write = 7.5 cycles (45 ns) per write. 90 MB / s

MISC

• 4-bytes range cross penalty = 3 cycles.
• Branch misprediction penalty = 4 cycles.

Links

Intel Pentium MMX at Wikipedia