Intel Pentium 4 (130 nm)
- L1 Data cache = 8 KB. 64 B/line, 4-way
- Trace cache: 12 Kuops, 8-way.
- L2 cache size = 128 KB. 64 B/line, 8-way, 2 Lines/Sector,
- TLB size = 64 items.
Pentium 4 - Celeron 2200 (130 nm, 2200 GHz, 128 KB L2) + DDR-266
4 KB pages mode (Windows XP)
| Size |
Latency |
Description |
| 8 K | 2 | TLB + L1 |
| 128 K | 18 | +16 (L2) |
| 256 K | 18 + 120 ns | + RAM |
| ... | 60 + 120 ns | +42 (TLB miss) |
- 64-bytes range cross penalty = 43 cycles.
- 4096-bytes range cross penalty = 67 cycles.
- L2 B/W (Read with 64 Bytes stride) = 3.12 cycles per cache line
- L2 B/W (Parallel Random Read) = 3.80 cycles per cache line
- RAM B/W (Read with 4 Bytes stride HW prefetch) = 1600 MB/s
- L1/L2 Write B/W (Write with any stride) = 12 cycles per cache line (64 bytes)
- RAM Write B/W (Write with any stride up to 64 Bytes) = 950 MB/s
Branch misprediction penalty = 22-24 cycles.