Intel Pentium 4 (180 nm)
- L1 Data cache = 8 KB. 64 B/line, 4-way
- Trace cache: 12 Kuops, 8-way.
- L2 cache size = 256 KB. 64 B/line, 8-way, 2 Lines/Sector,
- TLB size = 64 items.
Pentium 4 (Willamette, 180 nm, Socket 478, F.1.2, D0 stepping ) 1700 MHz (100.4 MHz * 17),
ASUS P4T-E(Intel i850 rev. A2), RDRAM, 384 MBytes, Dual Channels, 400 MHz,
CAS# (tRDRAM) = 10, tRCD = 9. two RDRAM PC800-40 modules and two PC800-45 modules.
4 KB pages mode (Windows 98 SE)
| Size |
Latency |
Description |
| 8 K | 2 | TLB + L1 |
| 256 K | 18 | +16 (L2) |
| ... | 53 + 155 ns | +35 (TLB miss) + RAM |
- 64-bytes range cross penalty = 43 cycles.
- 4096-bytes range cross penalty = 67 cycles.
- L2 Read B/W (with 64 Bytes stride) = 3.60 cycles per cache line (64 bytes)
- L2 Read B/W (Parallel Random Read) = 4.30 cycles per cache line (64 bytes)
- L1/L2 Write B/W (Write with 64 byte stride) = 11 cycles per cache line (64 bytes)
- RAM Read B/W (Read with 4 Bytes stride) = 1450 MB/s
- RAM Read B/W (Read with 64 Bytes stride) = 2200 MB/s
- RAM Read B/W (Parallel Random Read) = 60 ns per 2 cache lines (128 bytes) = 2100 MB/s
- RAM Write B/W (Write with any stride up to 64 Bytes) = 710 MB/s
Branch misprediction penalty = 22-24 cycles.