L1 Data cache = 16 KB. 64 B/line.
L2 cache size = 2 MB. 64 B/line, 2 Lines/Sector
TLB size = 64 items.
Size | Latency | Description |
---|---|---|
16 K | 4 | TLB + L1 |
256 K | 27 | +23 (L2) |
2 M | 60 | +33 (TLB miss) |
... | 60 + 122 ns | + RAM |
TLB size = 64 items.
Size | Latency | Description |
---|---|---|
16 K | 4 | TLB + L1 |
2 M | 27 | +23 (L2) |
128 M | 27 + 122 ns | + RAM |
... | 87 + 122 ns | +60 (TLB miss) |
64-bytes range cross penalty = 41 cycles.
4096-bytes range cross penalty = 95 cycles.
L2 B/W (Read with 64 Bytes stride) = 5.63 cycles per cache line
L2 B/W (Parallel Random Read) = 4.30 cycles per cache line
Branch misprediction penalty = 34-36 cycles.