Intel Silvermont

Intel Celeron N2840 (Silvermont), 2.166 GHz (Turbo Boost off), 22 nm. RAM: 2 GB, single DDR3-1333 CL9.

L1 Data Data cache = 24 KB. 64-byte line. 6-way.
L1 Instruction cache: 32 KB, 64-byte line, 8-way.
L2 Cache: 1024 KB (per 2 cores), 64-byte line, 16-way. Probably 2 lines are loaded from RAM for read access.

Instruction TLB L1I 4K: 48 entries, full-assoc.

L1 Data Cache Latency = 3 cycles for simple access via pointer
L1 Data Cache Latency = 3 cycles for access with complex address calculation (size_t n, *p; n = p[n]).
L2 Cache Latency = 14 cycles
RAM Latency = 14 cycles + 97 ns

2 MB pages mode

DATA TLB L1D 2M: 16 entries, 4-way.

4 KB pages mode (64-bit Windows)

DATA TLB L0D 4KB: 32 entries, full-assoc. Miss penalty = 7 cycles. Parallel miss: 8 cycles per access
DATA TLB L1D 4KB: 128 entries, 4-way. Miss penalty = 17 cycles. Parallel miss: 25 cycles per access
PDE cache = 16 items? Miss penalty = 24 cycles?

  Size        Latency       Increase   Description

  24 K     3                           
  64 K    10                       7   + 11 (L2)        
 128 K    12                       2   
 256 K    16                       4   + 7 (L0 TLB miss)
 512 K    19                       3   
   1 M    29                      10   + 17 (L1 TLB miss)
   2 M    34 +  49 ns      5 + 49 ns   + 97 ns (RAM)
   4 M    37 +  72 ns      3 + 23 ns
   8 M    38 +  84 ns      1 + 12 ns   
  16 M    38 +  91 ns           7 ns   
  32 M    38 +  95 ns           4 ns   
  64 M    50 + 105 ns     12 + 10 ns   + 24 ? (PDE cache miss)
 128 M    56 + 126 ns      6 + 21 ns
 256 M    59 + 152 ns      3 + 26 ns   + 97 ns (Page walk to RAM)
 512 M    61 + 171 ns      2 + 19 ns
   1 G    62 + 182 ns      1 + 11 ns

MISC

Branch misprediction penalty = 11-12 cycles

64-bytes range cross cycles = 6 cycles
4096-bytes range cross cycles = 9 cycles

L1 B/W (Parallel Random Read) = 1 cycles per one access

L2->L1 B/W (Parallel Random Read) = 4.6 per cache line
L2->L1 B/W (Read, 64 bytes step) = 4.0 cycles per cache line
L2->L1 B/W (Read, 8 bytes step - pointer chasing) = 4.0 cycles per access
L2->L1 B/W (Read, 64 bytes step - pointer chasing) = 11.5 cycles per access
L2->L1 B/W (Read, 128 bytes step - pointer chasing) = 14.0 cycles per access
L2 Write (Write, 64 bytes step) = 9 cycles per write (cache line)

RAM Read B/W (Parallel Random Read) = 25 ns / access. (128 bytes load per access ?)
RAM Read B/W (Read, 8-32 Bytes step) = 5800 MB/s
RAM Read B/W (Read, 32-128 Bytes step - pointer chasing) = 5800 MB/s (HW prefetch)
RAM Write B/W (Write, 8 Bytes step) = 2700 MB/s

Pipeline

Integer pipeline:

#	Name	Description
1	IF1	Instruction Fetch
2	IF2
3	IF3
4	ID1	Instruction Decode
5	ID2
6	ID3
7	AR1	Allocate Rename
8	AR2	Allocate Rename
9	RSV	Schedule
10	EX	Execute
11	RB1	Retire
12	RB2	Retire
13	RB3	Commit
14	RB4	Commit

7-Zip Benchmark

Turbo Boost on, 2580 MHz.

Note: MIPS and Effectiveness values are normalized with AMD K8 cpu.


7za b -mm=* -mmt1

7-Zip (a) [64] 15.14 : Copyright (c) 1999-2015 Igor Pavlov : 2015-12-31

      Intel(R) Celeron(R) CPU  N2840  @ 2.16GHz (30678)
CPU Freq:  2064  4266  2000  2064  2723  2723  2522  2522  2340

RAM size:    1930 MB,  # CPU hardware threads:   2
RAM usage:    225 MB,  # Benchmark threads:      1


Method           Speed Usage    R/U Rating   E/U Effec
                 KiB/s     %   MIPS   MIPS     %     %

CPU                      100   2522   2512
CPU                      100   2522   2511
CPU                       99   2501   2480   101   100

LZMA:x1           5992    99   2216   2191    89    88
                 25134    99   2061   2046    83    83
LZMA:x5:mt1       1519    99   1910   1898    77    77
                 23833   100   2010   2010    81    81
LZMA:x5:mt2       2126   143   1853   2657    75   107
                 23006    97   1997   1941    81    78
Deflate:x1       14216    98   1836   1805    74    73
                 68947    99   2157   2142    87    86
Deflate:x5        4945    96   1989   1904    80    77
                 70652    99   2209   2193    89    88
Deflate:x7        2028    97   2314   2247    93    91
                 71414    99   2232   2216    90    89
Deflate64:x5      5405    98   2372   2336    96    94
                 69907    99   2218   2187    89    88
BZip2:x1          3158    99   1920   1908    77    77
                 18204    99   1994   1973    80    80
BZip2:x5          2024    99   1706   1689    69    68
                  9144    99   1811   1795    73    72
BZip2:x5:mt2      3717   194   1600   3103    65   125
                 16913   181   1837   3320    74   134
BZip2:x7           711    99   1859   1843    75    74
                  9921    98   1977   1946    80    78
PPMD:x1           1934    93   2147   2001    87    81
                  1685    98   2034   1985    82    80
PPMD:x5           1349    99   2320   2287    94    92
                  1128    98   2166   2115    87    85
Delta:4         262292    99   1628   1612    66    65
                277054    99   1711   1702    69    69
BCJ             534428    99   2205   2189    89    88
                536441    99   2212   2197    89    89
AES256CBC:1      67803    95   1754   1666    71    67
                 68516    98   1716   1684    69    68
AES256CBC:2 

CRC32:1         335389    99   2470   2442   100    98
CRC32:4         998129    99   2251   2228    91    90
CRC32:8        1576744   100   2145   2138    86    86
CRC64           936587    99   1942   1918    78    77
SHA256           72372    99   1487   1476    60    60
SHA1            149399    97   1436   1398    58    56
BLAKE2sp    

CPU                       99   2508   2489
------------------------------------------------------
Tot:                     106   1978   2084    79    84

Links

Intel Silvermont at Wikipedia