Qualcomm Snapdragon

Qualcomm QSD8250 (Snapdragon) 1024 MHz (65 nm) - HTC HD2

L1 Data Cache = 32 KB. 32 B/line.
L2 Cache = 256 KB. 128 B/line.
Data L1 TLB size = 8 items.
Data L2 TLB size = 64 items.
Pipeline: 13 stages for load/store instructions, 10-12 stages for simple integer instructions.

4 KB pages mode

L2 Read B/W (32 Bytes stride) = 10 cycles per 32-byte cache line
RAM Read B/W (4 Bytes stride) = 300 MB/s
RAM Read B/W (128 Bytes stride) = 920 MB/s
RAM Read B/W (parallel random read) = 830 MB/s (128 byte cache line)
RAM Write B/W (4 - 16 Bytes stride) = 780 MB/s (Probably combining, No write allocate)