Sun UltraSPARC T1 (Niagara)
Configuration
Sun UltraSPARC T1 1000 MHz (Sun Fire T1000, RAM: 4 channel registered DDR2 PC2-4200).
Cache
- L1 Data cache = 8 KB. 4-Way, 16-byte lines, write-through (no-allocate on stores), virtually indexed / physically tagged.
- L1 Instruction cache = 16 KB, 4-Way, 32-byte line, pseudo random replacement.
- L2 cache size = 3 MB, 12-WAY. 64-byte line, writeback, 4 banks (with the bank selection based on physical
address bits 7:6), pseudo-least recently used (LRU) replacement.
- Data TLB size = 64 items, full assoc.
- Instruction TLB size = 64 items, Pseudo LRU.
- 48-bit virtual, 40-bit physical address space
- DRAM controller is banked four ways, with each
L2 bank interacting with exactly one DRAM controller bank. The DRAM controller is
interleaved based on physical address bits 7:6, so each DRAM controller bank must
have identical dual in-line memory modules (DIMM) installed and enabled.
- 8 cores * 4 threads per core
- Page sizes of 8 KB, 64 KB, and 512 KB and 4 MB.
- Four 144-bit DDR2-533 SDRAM interfaces
8 KB pages mode
| Size |
Latency |
Description |
| 8 K | 3 | TLB + L1 |
| 512K | 22 | + 19 (L1-Cache miss, L2 hit) |
| 3 M | 22 + 130ns | + 130ns (TLB miss) |
| ... | 22 + 250 ns | + 120ns RAM (L2-Cache Miss) |
- RAM Read B/W (4 Bytes stride) = 273 MB/s
- RAM Read B/W (64 Bytes stride) = 532 MB/s
Pipeline
| # |
Name |
Description |
| 1 | Fetch |
2 instructions fetched each cycle |
| 2 | Thread Select |
|
| 3 | Decode |
|
| 4 | Execute |
|
| 5 | Memory |
|
| 6 | Write Back |
|
Links
UltraSPARC T1 at Wikipedia