Applied Micro X-Gene

APM X-Gene1 (Storm), APM883208-X1. 2.4 GHz, 40 nm TSMC. RAM: 32 GB, dual DDR3-1600.

• L1 Data cache = 32 KB, 64 B/line, 8-WAY. Write-through with write-combining.
• L1 Instruction cache = 32 KB, ? B/line, 8-WAY.
• L2 Cache = 256 KB, 64 B/line, ?-WAY, shared by 2 cores.
• L3 Cache = 8 MB, 64 B/line, ?-WAY

• L1 Data Cache Latency = 5 cycles for simple access via pointer
• L1 Data Cache Latency = 6 cycles for access with complex address calculation (size_t n, *p; n = p[n]).
• L2 Cache Latency = 13 cycles
• L3 Cache Latency = 89 cycles
• RAM Latency = 89 cycles + 83 ns (for random RAM page)

• 4 wide out-of-order superscalar microarchitecture
• Decoding: 4 instructions
• pipes: branch, 2 integer ops / cycle, Separate load and store pipes, FPU/SIMD.

• APM883208-X1 - 2 DDR3 memory controllers with ECC
• APM883408-X1 - 4 DDR3 memory controllers with ECC

2 MB pages mode (64-bit Ubuntu)

• Data TLB L1: 20 items. full-assoc. Miss penalty = 10 cycles (L1 read), ? cycles (L2 read). Parallel miss: 11 cycles per access
• Data TLB L2: 1024 items. ?-way. Miss penalty = 27 (small block) - 36 cycles (big block). Parallel miss: 39 cycles per access

  Size        Latency       Increase   Description

  32 K     5                           
  64 K     9                       4   + 8 (L2)        
 128 K    11                       2   
 256 K    12                       1
 512 K    53                      41   + 76 (L3)
   1 M    72                      19
   2 M    81                       9
   4 M    85                       4   
   8 M    87 +  1 ns       2 +  1 ns   
  16 M    88 + 44 ns       1 + 43 ns   + 83 ns (RAM)
  32 M    89 + 65 ns       1 + 21 ns
  64 M    93 + 75 ns       4 + 10 ns   + 10 (L1 TLB miss)        
 128 M    96 + 79 ns       3 +  4 ns
 256 M    98 + 81 ns       2 +  2 ns
 512 M    99 + 82 ns       1 +  1 ns
   1 G    99 + 83 ns         +  1 ns
   2 G    99 + 83 ns         
   4 G   117 + 83 ns      18 +         + 36 (L2 TLB miss)
...

4 KB pages mode (64-bit Ubuntu)

• Data TLB L1: 20 items. full-assoc. Miss penalty = 6 cycles (L1 read), 9 cycles (L2 read). Parallel miss: 7 cycles per access
• Data TLB L2: 1024 items. ?-way. Miss penalty = 31 (L2 read) - 42 cycles (big block). Parallel miss: 39 cycles per access

  Size        Latency       Increase   Description

  32 K     5                           
  64 K     9                       4   + 8 (L2)        
 128 K    14                       5   + 9 (L1 TLB miss)        
 256 K    22                       8
 512 K    61                      39   + 76 (L3)
   1 M    80                      19
   2 M    89                       9
   4 M    94                       5   
   8 M   118 +  5 ns      24 +  5 ns   + 42 (L2 TLB miss)
  16 M   131 + 44 ns      13 + 39 ns   + 83 ns (RAM)
  32 M   141 + 65 ns      10 + 21 ns
  64 M   164 + 75 ns      23 + 10 ns
 128 M   191 + 79 ns      27 +  4 ns   + 76 (Page walk to L3)
 256 M   215 + 81 ns      24 +  2 ns
 512 M   238 + 82 ns      23 +  1 ns
   1 G   265 + 83 ns      27 +  1 ns
...

MISC

• Branch misprediction penalty = 19 cycles

• 16-bytes range cross penalty = 1 cycle
• 4096-bytes range cross - no additional penalty

• L1 B/W (Parallel Random Read) = 1 cycle per one access

• L2->L1 B/W (Parallel Random Read) = 2 cycles per cache line
• L2->L1 B/W (Read, 64 bytes step) = 2 cycles per cache line
• L2->L1 B/W (Read, 64 Bytes step - pointer chasing) = 13 cycles per cache line (no HW prefetch L2->L1)
• L2 Write (Write, 64 bytes step) = 1.25 cycles per write (L1 Write-through)

• L3->L1 B/W (Parallel Random Read) = 11.5 cycles per cache line
• L3->L1 B/W (Read, 64 bytes step) = 7 cycles per cache line
• L3->L1 B/W (Read, 64 Bytes step - pointer chasing) = 13.5 cycles per cache line (HW prefetch ?)
• L3 Write (Write, 64 bytes step) = 6.2 cycles per write

• RAM Read B/W (Parallel Random Read) = 17 ns / access line
• RAM Read B/W (Read, 8 Bytes step) = 7400 MB/s (4 KB pages)
• RAM Read B/W (Read, 8 Bytes step) = 12000 MB/s (2 MB pages)
• RAM Read B/W (Read, 64 Bytes step) = 16200 MB/s (2 MB pages)
• RAM Read B/W (Read, 64 Bytes step - pointer chasing) = 11000 MB/s (2 MB pages) (HW prefetch)
• RAM Write B/W (Write, 8 Bytes step) = 19000 MB/s (2 MB pages) (write-combining)

7-Zip Benchmark

Linux-3.13.0, THP off, gcc-5 -march=armv8-a -O2

Note: MIPS and Effectiveness values are normalized with AMD K8 cpu.

7z b -mm=* -mmt1

7-Zip (a) [64] 15.09 beta : Copyright (c) 1999-2015 Igor Pavlov : 2015-10-16
p7zip Version 15.09 beta (locale=en_US.UTF-8,Utf16=on,HugeFiles=on,64 bits,8 CPUs LE)

LE
CPU Freq:  2398  2398  2399  2399  2399  2399  2399  2399  2399

RAM size:   32197 MB,  # CPU hardware threads:   8
RAM usage:    211 MB,  # Benchmark threads:      1


Method           Speed Usage    R/U Rating   E/U Effec
                 KiB/s     %   MIPS   MIPS     %     %

CPU                      100   2399   2399
CPU                      100   2399   2399
CPU                      100   2399   2399   100   100

LZMA:x1           6762   100   2472   2472   103   103
                 23893   100   1924   1924    80    80
LZMA:x5:mt1       1577   100   1971   1970    82    82
                 22733   100   1912   1912    80    80
LZMA:x5:mt2       2841   168   2110   3550    88   148
                 22779   100   1916   1916    80    80
Deflate:x1       14973   100   1901   1901    79    79
                 67568   100   2090   2090    87    87
Deflate:x5        5636   100   2170   2170    90    90
                 68034   100   2096   2096    87    87
Deflate:x7        1942   100   2152   2152    90    90
                 68487   100   2109   2109    88    88
Deflate64:x5      5178   100   2238   2238    93    93
                 67724   100   2103   2103    88    88
BZip2:x1          3164   100   1912   1912    80    80
                 15148   100   1622   1622    68    68
BZip2:x5          2691   100   2247   2247    94    94
                 11962   100   2325   2325    97    97
BZip2:x5:mt2      4886   194   2105   4078    88   170
                 21169   183   2248   4114    94   171
BZip2:x7           794   100   2057   2057    86    86
                 12014   100   2334   2333    97    97
PPMD:x1           1900   100   1966   1966    82    82
                  1476   100   1738   1738    72    72
PPMD:x5           1220   100   2068   2068    86    86
                  1000   100   1874   1874    78    78
Delta:4         429259   100   2637   2637   110   110
                455963   100   2801   2801   117   117
BCJ             627239   100   2569   2569   107   107
                626106   100   2565   2565   107   107
AES256CBC:1      63166   100   1552   1552    65    65
                 61024   100   1500   1500    63    63
AES256CBC:2 

CRC32:1         258901   100   1885   1885    79    79
CRC32:4         569738   100   1272   1272    53    53
CRC32:8         723716   100    981    981    41    41
CRC64           569691   100   1167   1167    49    49
SHA256           95037   100   1939   1939    81    81
SHA1            214968   100   2012   2012    84    84
BLAKE2sp        130263   100   2866   2866   119   119

CPU                      100   2399   2399
------------------------------------------------------
Tot:                     110   2002   2215    84    92